Quantum Research Bits: September 12

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Is silicon the ideal substrate for qubits? It depends who you ask.

Making Qubits Last Longer

One of the big challenges in quantum computing is extending the lifetime of qubits, called coherence time, long enough to do something useful with them. Research is now focusing on how to increase this useful life and what factors can impact it.

This has led to very different conclusions about whether silicon is a good substrate choice for quantum chips. Researchers at the Supercomputing Quantum Materials and Systems Center (one of five quantum centers run by the US Department of Energy) say that silicon limits the lifespan of qubits through a process known as quantum decoherence.

The challenge has been to isolate the cause of this decoherence, as qubits must operate under near-perfect conditions. Measurements disturb the quantum process and all tests must be performed without destroying vital data. To make matters more difficult, all of this must be done at extremely low temperatures.

“We untangle the system to see how individual subcomponents contribute to qubit decoherence,” said Alexander Romanenko, CTO at DOE’s Fermi National Accelerator Laboratory, according to research. Remark. “A few years ago we realized that our [superconducting radio frequency] the cavities could be tools to assess the microwave losses of these materials with an accuracy of parts per billion and more.

By cooling a superconducting niobium RF cavity to hundreds of degrees above absolute zero, the researchers were able to isolate the electromagnetic waves. What they discovered was that with a silicon substrate, the waves dissipated more than 100 times faster than without silicon. They noted that sapphire or another material with less loss is a better choice for future quantum chips.


Fig. 1: Superconducting quantum processor, composed of thin layers deposited on a silicon substrate. Source: Fermilab

Imec, meanwhile, has developed a CMOS-compatible fabrication technique that uses stacked Josephson junctions, which have two electrodes separated by an insulating layer. In it, the researchers observe that one of the main problems lies in atomic-level defects at various interfaces that make up the junctions, which leads to a loss of energy from the qubit. By using evaporation and dual angle lift-off, Imec claims to be able to deliver extremely clean surfaces.

The next challenge, however, is to build qubits in sufficient volume, and this is where 300mm CMOS processes can help. “We have demonstrated in our lab superconducting qubits with coherence times greater than 100 µs and an average single-qubit gate fidelity of 99.94%,” imec researcher Tsvetan Ivanov said in a statement. Release. “These results are comparable to state-of-the-art devices, but for the first time they were achieved using CMOS-compatible fabrication techniques, such as state-of-the-art sputter deposition and subtractive etching.”

It remains to be seen whether this can be applied commercially. Another challenge is whether these qubits can be scaled down from millimeters to nanometers.

Quantum ML

How fast can you train an AI system? The answer depends on the amount of training data and the number of processing elements available to refine the algorithms to increase the accuracy of the results. So this got researchers from several institutions – the Technical University of Munich, Caltech, Los Alamos National Laboratory and the University of Maryland – thinking about how quickly this could be done using computers. quantum.

Their challenge was to find a way to improve generalization — by making accurate predictions based on unseen data — while using little training data. The results seem to be positive, using this approach improve the time to obtain results with sufficient accuracy. However, there is still a lot of work to do. But it solves a critical problem in machine learning, which is how much data is needed for machine learning to be useful, and how long it takes to produce and process that data.

Ed Sperling

Ed Sperling

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Ed Sperling is the editor of Semiconductor Engineering.

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